DFT (Design For Test) Engineer
at Etched
San Jose, onsite, senior, full time, USD 1,50,000–3,50,000 / year, 10+ years
posted 28 Feb 2026
- Scan insertion
- Perl
- Memory BIST
- SystemVerilog
- JTAG
- Synopsys DFT Compiler
- IEEE 1500
- Cadence Encounter Test
- Mentor Tessent
- Built-In Self-Test
- IEEE 1149.1
- Boundary scan
- TCL
- Python
About the role
Posted: 2026-02-28
About Etched
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
We are seeking a highly skilled and motivated Design For Testability (DFT) Engineer to join our dynamic team. The ideal candidate will be responsible for ensuring the robust testability of integrated circuits (ICs) from the design phase through to production. This role is crucial in improving the efficiency and effectiveness of our testing processes, thereby enhancing overall product quality.
What you would do
- Develop and implement robust Design for Test (DFT) architectures for ASIC and SoC designs to enhance test coverage, debug capability, and fault isolation.
- Integrate industry-standard DFT methodologies such as scan insertion, boundary scan, Built-In Self-Test (BIST), and Memory BIST (MBIST).
- Collaborate cross-functionally with design and verification teams to ensure DFT requirements are addressed early and consistently throughout the design cycle.
- Analyze test results and silicon debug data to provide design feedback and drive improvements in coverage, yield, and reliability.
- Create and execute comprehensive DFT verification plans to validate the correct implementation and functionality of all DFT features.
- Apply simulation-based and formal verification techniques to ensure high confidence in DFT logic correctness.
- Conduct internal DFT audits and design reviews to proactively identify and resolve gaps in testability or coverage.
- Support silicon bring-up, debug, and failure analysis during post-silicon validation to ensure successful product launch.
- Partner with test engineering teams to develop and optimize Automated Test Equipment (ATE) programs for volume production.
- Generate production-quality test patterns and ensure robust failure analysis capability in high-volume environments.
Read from jobs.ashbyhq.com, last seen 4d ago.