Post-Silicon Validation Engineer
at Etched
San Jose, onsite, senior, full time, USD 1,60,000–3,50,000 / year, 7+ years
posted 13 Oct 2025
- C
- Oscilloscopes
- Logic Analyzers
- UART
- PCIe
- SPI
- JTAG
- HBM
- DDR
- Ethernet
- BERT
- I2C
- Protocol Analyzers
- Python
About the role
Posted: 2025-10-13
About Etched
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
We are seeking a highly skilled and motivated Post Silicon Validation Engineer to join our dynamic team. The ideal candidate will be responsible for bringing up, validating, and characterizing ASICs from first silicon through the production ramp. This role is crucial in ensuring functional correctness, performance, and reliability of our AI/ML accelerator hardware, enabling successful deployment of our cutting-edge products.
What you would do
- Drive early bring-up of first silicon, including boot, initialization, and debug of ASICs.
- Perform deep-dive debug of silicon issues across RTL, firmware, and system levels.
- Collaborate closely with design, verification, and board teams to root-cause and resolve functional and electrical issues.
- Validate and characterize custom IP blocks and accelerator components.
- Execute functional and performance validation of compute units and specialized processing elements.
- Conduct IP-level and full-chip stress testing and corner case analysis to ensure robust operation.
- Develop and extend post-silicon validation infrastructure, automation, and test suites.
- Implement efficient result capture, analysis, and regression frameworks.
- Utilize lab instrumentation (oscilloscopes, analyzers, BERTs, pattern generators) for detailed signal and system characterization.
- Define validation strategies and coverage metrics across design blocks and subsystems.
- Partner with RTL, DFT, ATE, firmware, and system architecture teams to ensure smooth transition from pre-silicon verification to post-silicon validation.
- Provide critical feedback on test escapes, yield issues, and silicon errata, influencing silicon revisions and firmware/driver workarounds.
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