Formal Verification Engineer
at Tenstorrent
Santa Clara, California, United States; Spain, remote, senior, full time, USD 1,00,000–5,00,000 / year, 6+ years
posted 05 Oct 2026
- C++
- Coverage Analysis
- C
- Assertions
- RTL Verification
- SystemVerilog
- Formal Verification
- Constraints
- Property Checking
- Assumptions
- Tcl
- SVA
- Python
About the role
Posted: 2026-10-05
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
Tenstorrent is looking for a Formal Verification Engineer to help ensure the correctness of our next generation of high-performance RISC-V CPUs and AI compute platforms. You’ll use formal methods to prove complex hardware behavior, uncover corner cases that simulation may miss, and give architects and RTL designers confidence in the correctness of their designs. You’ll work closely with CPU architects, RTL designers, and other DV engineers to develop properties, build formal verification environments, analyze failures, and drive issues to closure. This is a hands-on opportunity to apply formal techniques to challenging problems in modern processor design.
This role is remote, based out of North America or Spain.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
What they are looking for
- A verification engineer who enjoys solving complex problems and finding bugs that are difficult to expose through traditional simulation.
- Comfortable thinking about hardware behavior in terms of properties, invariants, assumptions, assertions, and proofs.
- A strong debugger who can analyze counterexamples, understand RTL behavior, and determine the root cause of failures.
- Collaborative and curious, with an interest in working closely with architects and RTL designers to improve design quality.
- Excited by the challenges of verifying high-performance CPUs and complex digital hardware.
What We Need
- 6+ years of experience in design verification, formal verification, or related RTL verification for CPUs, SoCs, ASICs, or complex digital designs.
Read from job-boards.greenhouse.io, last seen 4d ago.