Physical Design Engineer
at Etched
Austin, hybrid, senior, full time, USD 2,00,000–3,75,000 / year, 5–10 years
posted 16 Apr 2026
- Scan insertion
- IR drop
- PrimeTime
- Low power design
- CTS
- Floorplanning
- EM/antenna analysis
- Routing
- UPF
- Tempus
- Voltus
- Cadence Genus
- Power verification
- RTL synthesis
- ATPG
- GDSII sign-off
- Cadence Innovus
- Synopsys Fusion Compiler
- Placement
- Synopsys ICC2
- Formal verification
- Python
About the role
Posted: 2026-04-16
About Etched
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Etched is looking for exceptional Physical Design engineers to join our team. In this role, you will own block-level implementation and verification, drive timing closure and PPA optimization, supervise 3rd party design work, and help improve our design flows and iteration speed.
What you would do
- Deeply understand what is involved in physical design
- Running PD flows to close blocks, support ASIC infrastructure, automate PD flows, improve CAD infrastructure
- Collaborate with RTL Designers and provide Physical Design feedback to improve PPA
- Drive dashboards that show the convergence of projects related to PD
- Optimize tool flows, working with EDA vendors to incorporate the latest features
- Accountable for block level closure
- Supervise the outsourcing of physical design to a 3rd party service
You may be a good fit if you have
- 5-10+ years of previous experience with PD
- Tools, flow, and design methodology from RTL synthesis to GDSII sign-off
- Experience with back-end design and timing closure on advanced process nodes (5nm and below)
- Experience with Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler) automated RTL-to-GDSII flows
- Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.)
- Experience with UPF-based low power design methodology, power verification,synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis
- Deeply creative and able to think from first principles
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