Design Verification Engineer - SoC
at Etched
Austin, hybrid, full time, USD 1,50,000–3,50,000 / year
posted 16 Apr 2026
- SystemVerilog
- Compute accelerators
- Simulation
- Memory hierarchies
- Pipelines
- Interconnects
- RTL
- ASIC design flows
- Modeling
- Python
About the role
Posted: 2026-04-16
About Etched
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
We are seeking a Design Verification Engineer to join our Systems/Performance Verification team. You will ensure the custom IPs powering our chips — including systolic arrays, DMA engines, and NoCs — are robust, high-performance, and silicon-ready. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges. You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack.
What you would do
- Work closely with architects and RTL designers on verifying the performance features of the design and correlating with performance models (both pre-silicon and post-silicon).
- Work closely with software and application developers on identifying performance bottlenecks and tuning the software.
- Develop test plans and test infrastructure/tools for performance tuning, correlation, and verification.
- Improve and maintain the architectural performance models.
- Develop tests in SystemVerilog, Python, or vectors to debug and correlate the RTL and performance model.
- Develop SystemVerilog or Python-based checkers for verifying the performance features.
- Develop coverage monitors and analyze coverage to ensure all performance features are covered.
- Debug performance issues and conduct performance tuning on silicon.
- Drive end-to-end performance tuning, ensuring optimal hardware utilization, software efficiency, and architectural alignment across the ASIC design lifecycle.
You may be a good fit if you have
- Strong understanding of digital design, RTL, and ASIC design flows.
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